Job Description

Role : Mixed-Signal Design Verification Engineer

Location : San Jose, CA (100% Onsite)

Job Type : Contract

Interview : Phone/Skype

We are looking for a Mixed-Signal Design Verification Engineer with expertise in System-Verilog , AMS Verification , and Synopsys/Cadence EDA tools. Responsibilities include developing Analog/Mixed-Signal models, creating UVM Testbenches, running simulations, and collaborating with designers to refine functional specifications. Strong knowledge of digital and mixed-signal control loops , timing analysis , and clock domain constraints is essential.

**Cadence #Synopsys #EDA #**Analog #Python #DesignVerification #SystemVerilog #AMS #Verification #MixedSignalDesign #C2CHiring ##MixedSignal #UVM

Additional Information

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