Job Description

Role: Physical Design (STA) Engineer
Location: San Jose CA – Full onsite
Interview: Phone/Skype
Job Type: Contract

JOB DESCRIPTION
• Contribute to and own large partitions, sub-chips, and/or full chip from synthesis to place and route through all signoffs including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification.
• Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
• Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
• Understanding of constraints generation, STA, timing optimization, and timing closure.
• Experience in EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC.
• Understanding of design tradeoffs for power, performance, and area.
• Proficient understanding of CTS and different clock building techniques
• Experience with multi-voltage, multi-clock, multi-domain, and low power designs.
• Knowledge of formal equivalency checks, LP, UPF, reliability, SI, and noise
• Full Chip/Sub Chip design planning experience using Cadence EDA tools.
• Large SoC design tape-out experience in the latest foundry process nodes.
• Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
• Strong fundamentals in VLSI design
• Strong problem-solving and data analysis skills
• Strong skills using scripting languages such as Perl, TCL, Python.
Synopsys/Cadence EDA Tools (Priority: 1)
Synopsys/Cadence STA Tools (Priority: 1)
PrimeTime-Si (Priority: 1)

Additional Information

All your information will be kept confidential according to EEO guidelines.