Sr Logic Design RTL Engineer

PDDN INC.

Sr Logic Design RTL Engineer

Santa Clara, CA
Full Time
Paid
  • Responsibilities

    Job Description

    Role: Sr Logic Design (RTL) Engineer

    Location: Santa Clara, CA (Remote and Hybrid options available)

    Job Type: Contract

    Interview: Phone/Skype

    Join our team to perform detailed block design and develop RTL code for cutting-edge IP development!

    Key Responsibilities:

    • Develop HW architecture and write RTL code for IP development and integration

    • Perform Lint checks, CDC tests, and create timing constraint files

    • Support verification and physical design teams

    • Execute low power design (UPF/CPF) and integrate top-level RTL

    • Collaborate with cross-functional teams to meet performance, power, and area goals

    Experience & Skills:

    • Bachelor’s or Master’s in Electrical/Computer Engineering or related field

    • 12+ years in Logic (RTL) Design

    • Proficiency in Verilog/System Verilog/VHDL

    • Strong fundamentals in VLSI design, digital design architecture, and scripting (Perl, TCL, Python)

    • Excellent communication and collaboration skills

    Preferred:

    • Experience with GPIO, UART, SPI, JTAG, I2C, and high-speed serial protocols (PCIe/USB/Ethernet)

    • Role: Sr Logic Design (RTL) Engineer Location: Santa Clara, CA (Remote and Hybrid options available) Pay Rate: $78/hr C2C Job Type: Contract Interview: Phone/Skype

    Join our team to perform detailed block design and develop RTL code for cutting-edge IP development!

    Key Responsibilities:

    • Develop HW architecture and write RTL code for IP development and integration

    • Perform Lint checks, CDC tests, and create timing constraint files

    • Support verification and physical design teams

    • Execute low power design (UPF/CPF) and integrate top-level RTL

    • Experience & Skills:

    • Bachelor’s or Master’s in Electrical/Computer Engineering or related field

    • 12+ years in Logic (RTL) Design

    • Proficiency in Verilog/System Verilog/VHDL

    • Strong fundamentals in VLSI design, digital design architecture, and scripting (Perl, TCL, Python)

    • Excellent communication and collaboration skills

    • Preferred:

    • Experience with GPIO, UART, SPI, JTAG, I2C, and high-speed serial protocols (PCIe/USB/Ethernet)

        • Collaborate with cross-functional teams to meet performance, power, and area goals
  • Qualifications

    Additional Information

    All your information will be kept confidential according to EEO guidelines.